The present invention relates to a high-withstand-voltage integrated circuit having two or more power sources at different potentials. Such circuits have low loss and are suited for use under severe operating conditions with power-source voltage variations and surges as typically present in automotive electrical systems.
A conventional high-withstand-voltage integrated circuit (IC) in which a vertical power MOSFET, its control circuit and a protective circuit are integrated in one semiconductor substrate is described, e.g., by M. Glogolja et al., "Smart-SIPMOS--An Intelligent Power Switch", Conference Record, IEEE Ind. Appl. Soc. Annual Meeting, pp. 429-433 (1986). As illustrated by FIG. 2, such a high-withstand-voltage IC has five terminals, namely a main power-source terminal V.sub.CC, a ground terminal GND, a power-output terminal P.sub.OUT, a signal-input terminal S.sub.IN, and a signal-output terminal S.sub.OUT. The circuit is divided into a low-potential circuit L which is supplied with power from a low-potential power source VL, and a high-voltage circuit N which is connected to the main power source V.sub.CC. The low-potential circuit L includes a digital-circuit section that inputs and outputs signals to and from external sources, and a logic circuit for control. The high-voltage circuit N includes an output-stage power switching element Q1, implemented by an n-channel power MOSFET, a drive circuit for the output-stage power element Q1, and an analog monitoring circuit for checking voltage, current, temperature, and feedback.
FIG. 3(a) and 3(b) represent cross-sectional portions of a typical IC-chip implementation of a conventional high-withstand voltage circuit.
Formed on an epitaxial n- layer 2 on an n+ substrate substrate 1 are a vertical power MOSFET 21, a p-channel MOSFET 22, an n-channel MOSFET 23, a Zener diode 24, a high-withstand-voltage p-channel MOSFET 25, and a high-withstand-voltage n-channel MOSFET 26. In the vertical MOSFET 21, a p-well 41 is formed selectively at the surface of the n- layer 2, an n+ source layer 51 is formed at the surface of the p-well, and a gate electrode 71 is between the exposed portions of the n+ source layer 51 and the n- layer 2, on a gate oxide film 6. A drain electrode 11 of MOSFET 21, on the back side of the substrate 11, is connected to the main (battery) power source V.sub.CC, and a source electrode 12 is insulated by the gate electrode 71 and inter-layer insulation films 8 and makes contact with both the source layer 51 and the p-well 41.
In the p-channel MOSFET 22, a p-source layer 42 and a p-drain layer 43 are at the surface of the n- layer 2, a gate electrode 72 is on the gate oxide film 6 over the source and drain layers 42 and 43 which make contact with respective source and drain electrodes 13 and 14.
In the n-channel MOSFET 23, a p-well 44 is at the surface of the n- layer 2, an n+ source layer 52 and an n+ drain layer 53 are formed selectively at the surface of the n- layer 2, and a gate electrode 73 is on a gate oxide film 6 over the source and drain layers 52 and 53 which make contact with respective source and drain electrodes 15 and 16.
The Zener diode 24 is composed of a p-anode layer 45 formed at the surface of the p- layer 2, and an n-cathode layer 54 formed at the same surface. The anode and cathode layers 45 and 45 make contact with respective anode and cathode electrodes 17 and 18.
Similar to the p-channel MOSFET 22, the high-withstand-voltage p-channel MOSFET 25 has a p-source layer 46, a p-drain layer 47, a gate electrode 74, a source electrode 19, a drain electrode 20, and a gate oxide film 6. The MOSFET 25 also has a voltage-withstand structure including an extended portion of the gate electrode 74 in the channel section between the source layer 46 and the drain layer 47, and further including the drain electrode 20, the thick-oxide film 4 and the insulation film 8.
Similar to the n-channel MOSFET 23, the high-withstand-voltage n-channel MOSFET 26 has an n+ source layer 55, formed at the surface of a p-well 48. An n- drain layer 57 with a low impurity concentration surrounds an n+ drain layer 56, and a voltage-withstand structure is included, consisting of an extended portion of the gate electrode 75 between the channel portion and the drain electrode 30. The thick oxide film 4 and the insulation film 8 are formed as in the MOSFET 25. The source electrode 29 makes contact with both the n+source layer 55 and the p-well 48. The drain electrode 30 makes contact with the n+ drain layer 56.
The conventional high-withstand voltage IC as described has several drawbacks. The active elements constituting the high-withstand-voltage circuit N are large-size elements such as, e.g., the high-withstand-voltage p-channel MOSFET 25 and the n-channel MOSFET 26 shown in FIG. 3(b). This results in increased chip area and cost. In the low-potential circuit L, the p-channel MOSFET 22, which must have high withstand voltage against the n- layer 2, requires the formation of a deep p-source layer 42 and a p-drain layer 43 by diffusion. This results in increased size and decreased integration density. When the main power-source voltage V.sub.CC, applied to the drain electrode 11, varies due to voltage surges, the voltage in the source layer 42 of the p-channel MOSFET in the low-potential circuit L, the voltage in the drain layer 43, and the voltage in the n- layer 2 vary similarly. Moreover, a displacement current due to the junction capacitance and the voltage fluctuation may cause malfunctioning. For protection against over-currents and detection of loads, a comparator in the high-withstand-voltage circuit N is required to monitor the potential P.sub.OUT in the power output. Since P.sub.OUT generally varies from near the main power source V.sub.CC to GND, the comparator has low detection accuracy.
The present invention, described below, addresses the above-mentioned drawbacks and provides a low-cost, reliable high-withstand-voltage IC.